Veriflat is a nice little Perl system for flattening structural Verilog designs. By structural, I mean hierarchical designs formed by module definitions and module instantiations and having only the basic gates at the leaf level. Currently, these basic gates are supported: and, or, xor, not, buf. No assignment statements please. And yes, only one module per Verilog file. And module names and file names should match.
What's cool is that parameters are supported. So are the generate statements. Look at the example, bvlshr.v or logical shift right, provided in the package.
How to use
Download the package: veriflat-327.tar.gz
It contains the main Perl script, veriflat.plx, along with two
supporting Perl modules, and Verilog files comprising the bvlshr
example.
The command ”veriflat.plx bvlshr.v 19” will read bvlshr.v and
all other modules instantiated within it, and spit out flattened
19-bit bvlshr.
If you want to install this script to some directory, please copy the Perl modules (i.e. *.pm files) along with the main script.