quan m. nguyen


Microthread Information and Register Visualization (MIRV) Tool


Hwacha is a decoupled vector-fetch data-parallel accelerator described by Lee et al. implemented for the RISC-V ISA. From the programmer's perspective, Hwacha operates with the concept of microthreads. Microthreads are units of computation that complete one operation in a vector of many elements. The programmer only needs to tell Hwacha how many integer registers and floating point registers to allocate for each microthread. They have just about every capability of a typical RISC-V core (e.g. Rocket). However, the implementation is very different. Hwacha, in its current implementation, allocates registers across 8 banks of 256 registers (of 65-66 bits each). The organization of registers can be confusing for beginners, hence this tool.

You can obtain more information on Hwacha by consulting its manual.

How to use this tool

First, specify the number of banks and the number of registers per bank. These are (presently) hard-coded values in Hwacha's implementation, but parameterization is underway.

In CS 250, we developed an extension to Hwacha that would allow it to support packing smaller-width floating-point values into the floating-point registers based on user-configured packing for a "global" precision. The original version of MIRV was designed with this in mind, and is located here.

Then, specify the number of integer registers and double-precision floating-point registers that you will need to have. These are the arguments to the vsetcfg instruction. This tool does not quite capture the edge cases yet.

In CS 252, we developed further, introducing the notion of multiple precisions within the same configuration, allowing arbitrary combinations of double-precision, single-precision, and half-precision floating-point registers in addition to the usual integer registers. The updated interface reflects this change.

To set the number of single-precision and half-precision floating-point registers, specify the number of each register as the arguments to the vsetucfg instruction. The number of half-precision floating-point registers desired is left-shifted six bits and bitwise-ORed to the number of single-precision floating-point registers desired. There may be up to 32 integer registers (including x0, hardwired to zero and not allocated), and up to 32 floating-point registers total, selected from any type (double, single, half).

MIRV Interface

Hwacha Hardware Parameters

Number of banks:

Number of registers per bank:

Hwacha Software Parameters

Number of integer registers:

Number of double-precision floating-point registers:

Number of single-precision floating-point registers:

Number of half-precision floating-point registers:

Diagnostic Information

Code snippet

vsetucfg x1, ( << 6) |
vsetcfg x1, ,

Microthreads (maxvl):

Registers available:

Registers used:

Register file utilization:

Split locations:


(Enter some parameters and press "Update.")