quan m. nguyen

Research

Microthread Information and Register Visualization (MIRV) Tool - Old version

Newer Version

This is the old version of the MIRV tool; the new one can be found here.

Introduction

Hwacha is a decoupled vector-fetch data-parallel accelerator described by Lee et al. implemented for the RISC-V ISA. From the programmer's perspective, Hwacha operates with the concept of microthreads. Microthreads are units of computation that complete one operation in a vector of many elements. The programmer only needs to tell Hwacha how many integer registers and floating point registers to allocate for each microthread. They have just about every capability of a typical RISC-V core (e.g. Rocket). However, the implementation is very different. Hwacha, in its current implementation, allocates registers across 8 banks of 256 registers (of 65-66 bits each). The organization of registers can be confusing for beginners, hence this tool.

You can obtain more information on Hwacha by consulting its manual. (The joke is that there is no manual.)

How to use this tool

First, specify the number of banks and the number of registers per bank. These are (presently) hard-coded values in Hwacha's implementation, but parameterization is underway.

Then, specify the number of integer registers and floating-point registers that you will need to have. These are the arguments to the vsetcfg instruction. Note that you must have at least one floating-point register. This tool does not quite capture the edge cases yet.

In CS 250, we developed an extension to Hwacha that would allow it to support packing smaller-width floating-point values into the floating-point registers. You can specify the precision/packing. This is the argument to the vsetucfg instruction, which sets the upper 20 or 52 bits of the register with the configuration information. (vsetcfg is another way of setting the lower 12 bits, as in an immediate instruction, with two numbers, the number of xregs and fregs.) The precision number is coded as such:

Precision	Bits	vsetucfg Encoding
Double	64	0
Single	32	1
Half	16	2

MIRV Interface

Hwacha Hardware Parameters

Number of banks:

Number of registers per bank:

Allocation method: old new

Hwacha Software Parameters

Number of integer registers:

Number of floating-point registers:

Register packing / precision: 1 / double 2 / single 4 / half

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Diagnostic Information

Code snippet

vsetucfg x1,
vsetcfg x1, ,

Microthreads (maxvl):

Registers available:

Registers used:

Register file utilization:

Stride:

Visualization