UC Berkeley EECS 151LA Technical Report
This page is also available in:
UC伯克利EECS 151LA项目技术报告：一个五级流水线的RISC-V CPU
UC Berkeley EECS 151LA Project Technical Report: A 5-Stage RISC-V CPU
EECS 151: Introduction to Digital Design and Integrated Circuits, Professor John Wawrzynek
EECS 151LA: Application Specific Integrated Circuits Laboratory, TA Lux Zhang
2023 Spring Semester
The Abstraction Workshop - Fubuki and Marco
(English version TODO)
