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   Author  Topic: Memory access doubt  (Read 537 times)
kirru
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Posts: 34
Memory access doubt  
« on: Oct 20th, 2020, 12:09am »
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https://cse.buffalo.edu/~stevko/courses/cse490/spring11/files/cache2.pdf  
In this pdf last slide, serial vs parallel cache access
 
 they said that in parallel access  
1. High bandwidth required for memory path
2. Complexity of handling parallel paths can slow cache access time.  
 
Didn't get both reasons. Can any one please elaborate on it.
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